IN74HC174A datasheet(6/6 Pages) INTEGRAL | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS

Part #	IN74HC174A

Description	Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS

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Manufacturer	INTEGRAL [Integral Corp.]

Direct Link	http://www.iksemi.com/

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IN74HC174A

6

INTEGRAL

CHIP PAD DIAGRAM

Chip marking :15HC174

Location of marking (mm): left lower corner x = 0.110, y = 0.870; right lower corner x = 0.240, y = 0.900

Chip thickness: 0.46

± 0.02 mm

PAD LOCATION

Location (left lower corner), mm

Pad No

Symbol

X

Y

Pad size, mm

01

Reset

0.115

0.340

0.12

×0.12

02

Q0

0.115

0.140

0.12

×0.12

03

D0

0.325

0.115

0.12

×0.12

04

D1

0.580

0.115

0.12

×0.12

05

Q1

0.850

0.115

0.12

×0.12

06

D2

1.145

0.115

0.12

×0.12

07

Q2

1.345

0.140

0.12

×0.12

08

GND

1.370

0.355

0.12

×0.16

09

Clock

1.365

0.815

0.12

×0.12

10

Q3

1.355

1.045

0.12

×0.12

11

D3

1.155

1.065

0.12

×0.12

12

Q4

0.880

1.065

0.12

×0.12

13

D4

0.620

1.065

0.12

×0.12

14

D5

0.320

1.065

0.12

×0.12

15

Q5

0.125

1.045

0.12

×0.12

16

Vcc

0.115

0.660

0.12

×0.19

Note: Location is given as per passivation layer

01

08

02

09

03

10

04

1.6 + 0.03

11

05

15

Chip marking

12

06

16

13

07

14

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IN74HC174A Datasheet(PDF) 6 Page - Integral Corp.

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