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PM5309 Datasheet(PDF) 1 Page - PMC-Sierra, Inc |
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PM5309 Datasheet(HTML) 1 Page - PMC-Sierra, Inc |
1 / 2 page PM5309 Released Multi-rate Telecom Backplane SERDES for 2.5 Gbit/s Interconnect TBS 2488 PMC-2021208 (R4) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2005 FEATURES • High performance backplane interface and cross-connect for 2.5G line cards in SONET/SDH systems. • Provides one low-speed parallel TelecomBus interface operating at 32 bits x 77.76 MHz. • Provides three high-speed multi-rate serial backplane interfaces. • Supports CLOS and memory-based switch fabric systems. • Supports linear, UPSR, and BLSR protection strategies. SWITCHING CAPACITY • Implements a 10G memory switch fabric with STS-1/AU-3 switching granularity in a single device. • Supports non-blocking anycast switching between any of the serial or parallel interfaces. • Provides two pages of connection memory with software and hardware controlled hitless page swaps at frame boundaries. • Provides integrated delay management that allows for arbitrary SONET/SDH frame alignments on each ingress serial link. SERIAL PORT FUNCTIONS • Supports three RASIO 3G high-speed serial backplane interfaces for interfacing with SONET/SDH cross-connects, framers, mappers, and other TBS™ 2488 devices. • Each high-speed serial backplane interface is capable of independent operation at 4x622 Mbit/s scrambled NRZ SONET/SDH, 4x777 Mbit/s Serial TelecomBus, or 1x2488 Mbit/s scrambled NRZ SONET/SDH. • High-speed serial RASIO compatible with CML, LVDS, and LVPECL. • Supports nibble and di-bit slicing on 622 Mbit/s links for sliced switching architectures. PARALLEL PORT FUNCTIONS • Supports one 32-bit or four 8-bit 77.76 MHz TelecomBus interfaces to interface with parallel TelecomBus framers and mappers. • Integrated pointer interpreter reduces complexity of external framers and mappers by asserting payload, J0, and J1 indications on the outgoing TelecomBus interface. • Allows insertion and extraction of TOH bytes through a dedicated low speed serial interface. BLOCK DIAGRAM ESSI Link Framing & Monitoring Rx RASIO Pointer Interpreter & Delay Mgmt ESSI Link Framing & Monitoring Rx RASIO Pointer Interpreter & Delay Mgmt Connection Memory and Control T elecomBus Monitor & Byte Interleave ESSI Link Framing & Monitoring Rx RASIO Pointer Interpreter & Delay Mgmt ESSI Link Generator Tx RASIO TxP1[4:1] TxN1[4:1] ESSI Link Generator Tx RASIO TxP2[4:1] TxN2[4:1] ESSI Link Generator Tx RASIO TxP3[4:1] TxN3[4:1] T elecomBus Signal Generator & Byte De- Interleave Overhead Extract CSU (3) Overhead Insert JT AG Interface Microprocessor Interface RxP1[4:1] RxN1[4:1] RxP2[4:1] RxN2[4:1] RxP3[4:1] RxN3[4:1] OD[4:1][7:0] ODP[4:1] OPL[4:1] OJ0J1[4:1] OPAIS[4:1] OD[4:1][7:0] ODP[4:1] OPL[4:1] OJ0J1[4:1] OPAIS[4:1] STS-1 / AU-3 Cross-Connect SYSCLK ITOHD ITOHEN OTOHD OTOHFP OTOHCLK ITOHFP ITOHCLK |
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