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NCP1205P Datasheet(PDF) 14 Page - ON Semiconductor |
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NCP1205P Datasheet(HTML) 14 Page - ON Semiconductor |
14 / 20 page NCP1205 http://onsemi.com 14 As soon as the system recovers from the error, e.g. FB is back within its regulation area, the IC operation comes back to normal. To avoid any system thermal runaway, another internal 8 x 128 ms delay is combined with the previous 128 ms. It works as follows: the 128 ms delay is provided to account for any normal transients that engender a temporary loss of feedback (FB goes toward ground). However, when the 128 ms period is actually over (the feedback is definitively lost) the IC stops the output driving pulses for a typical period of 8 x 128 ms. During this mode, the rest of the functions are still activated. For instance, in lack of pulses, the self–supplied being no longer provided, the start–up source turns on and off (when reaching the corresponding UVLOL and UVLOH levels), creating an hiccup waveform on the Vcc line. As soon as the feedback condition is restored, the 8 x 128 ms is interrupted and, in synchronism with the Vcc line, the IC is back to normal. The following diagrams show how this mechanism takes place when FB is down to zero (optocoupler opened) or up to Vcc (optocoupler shorted). If we assume that the error is permanently present, then a burst mode takes place with a 128/8 x 128 = 12.5% duty–cycle. The real transmitted power is thus: PoutBURST + 1 2 ·Lp·Ip2 ·Fsw ·DutyBURST Overvoltage Detection (OVP) OVP detection is done differently on the DIP8 and DIP14 versions. In the DIP8, because of available pin count, the OVP is accomplished by monitoring the Vcc voltage. On the DIP14, the device also monitors the Vcc level but in parallel, the triggering point has been pin–out to allow precise OVP selection. This pin can also be used to externally latch–off the IC. As mentioned, Over Voltage Conditions are detected by monitoring the Vcc level. Figure 17 describes how three 10 V zener plus one 5.0 V zener are connected in series together with a 18 k Ω to ground. As soon as Vcc exceeds 40 V typical, a current starts to flow in the 18 k resistor. When the voltage developed across this element exceeds 2.8 V, an error is triggered and immediately latches the IC off. In lack of switching pulses, the Vcc capacitor is no longer refreshed by the auxiliary supply and slowly discharges toward ground. When the Vcc level crosses UVLOL, a new startup sequence occurs. If the OVP has gone, normal IC operation takes place. For different OVP levels, the comparator input is accessible through pin 6 in the DIP14 option. Figure 17. In the DIP8 Version, the OVP Pad is not Pinned Out and is Available with DIP14 Devices Only + 2.8 V Latched OVP 5 V 10 V 18 k 10 V 10 V 6 5 4 3 2 1 7 VCC 8 2 k OVP Protecting Pin 1 Against Negative Spikes As any CMOS controller, NCP1205 is sensitive to negative voltages that could appear on it’s pins. To avoid any adverse latch–up of the IC, we strongly recommend inserting a 15 k resistor in series with pin 1 and the high–voltage rail, as shown in Figures 18 and 19. This 15 k resistor prevents from adversely latching the controller in case of negative spikes appearing on the bulk capacitor during the power–off sequence. Please note that this resistor does not dissipate any continuous power and can therefore be of low power type. Two 8.2 k can also be wired in series to sustain the large DC voltage present on the bulk. |
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