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NCP1205 Datasheet(PDF) 13 Page - ON Semiconductor |
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NCP1205 Datasheet(HTML) 13 Page - ON Semiconductor |
13 / 20 page NCP1205 http://onsemi.com 13 Figure 15. This Typical Arrangement Allows for an Easy Fault Detection Management – + V(–) Ri 50 k – + + + + 2R R OCP Circuitry Current Setpoint Vfb Vlow 1.5 V Vfb V1 2.5 V VHIGH = 3 V VLOW = 5 mV 1 2 3 5 6 7 Rf 150 k Monitor To illustrate how the system reacts to a variable FB level, we have entered the above circuit into a SPICE simulator and observed the output waveforms. When FB is within regulation, the error flag is low. However, as soon as FB leaves its normal operating area, the OPAMP can no longer keep the V(–) point and either goes to the positive top or down to zero: the error flag goes high. Because of the large amount of delay necessary for this 128 ms operation, the capacitor used for the timing is Ct, connected from ground to pin 5. In normal VFM operation, this timing capacitor serves as the VCO capacitor and the error management circuit is transparent. As soon as an error is detected (error flag goes high), an internal switch routes Ct to the 128 ms generator. As a first effect, the switching frequency is no longer controlled by the VCO (if the error appears during VFM) and the system is relaxed to natural BCM. The capacitor now ramps up and down to be further divided and finally create the 128 ms delay. Figure 16. By Monitoring the Internal Virtual Ground, the System can Detect the Presence of a Fault Regulation Area OCP Condition Error Flag Virtual Point FB 1.5 V 1.000 M 3.000 M 5.000 M 7.000 M 9.000 M 6.500 4.500 2.500 500.0 M |
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