LC87F57C8A

Ver.1.00

11/27

Port Output Configuration

Output configuration and pull-up resistor options are shown in the following table.

Input is possible even when a port is in output mode.

Terminal

Option

applies to:

Option

Output Format

Pull-up resistor

1

CMOS

Programmable (Note 1)

P00 - P07

each bit

2

Nch-open drain

None

1

CMOS

Programmable

P10 - P17

P20 - P27

each bit

2

Nch-open drain

Programmable

1

CMOS

Programmable

PA2 - PA5

PB0 - PB7(*)

PC0 - PC7

each bit

2

Nch-open drain

Programmable

P70

-

None

Nch-open drain

Programmable

P71 - P73

-

None

CMOS

Programmable

P80 - P82

-

None

Nch-open drain

None

PWM0, PWM1

-

None

CMOS

None

XT1

-

None

Input only

None

XT2

-

None

Output for 32.768kHz crystal oscillation

None

Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 - P03, P04 - P07).

(*) When in parallel interface mode, PB0 - PB7 output format is CMOS, regardless of any selected option.

Note:

To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2,

and VSS3 should connect to each other and they should also be grounded.

Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor.

VSS1 VSS2 VSS3

VDD1

VDD2

VDD3

Power

Supply

Back-up

capacitor

LSI