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NCP5331 Datasheet(PDF) 30 Page - ON Semiconductor |
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NCP5331 Datasheet(HTML) 30 Page - ON Semiconductor |
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30 / 38 page  NCP5331 http://onsemi.com 30 NOTE: The value of CA1 is too low and the loop gain/ bandwidth too high. COMP moves too quickly, which is evident from the small spike in its voltage when the load is applied or removed. The output voltage transitions more slowly because of the COMP spike. Figure 38. COMP Tuning, Bandwidth Too Low Figure 39. COMP Tuning, Bandwidth Too High NOTE: The value of CA1 is too high and the loop gain/ bandwidth too low. COMP slews too slowly which results in overshoot in VCORE. Figure 40. COMP Tuning, Bandwidth Optimal NOTE: The value of CA1 is optimal. COMP slews quickly without spiking or ringing. VCORE does not overshoot and monotonically settles to its final value. 8. Error Amplifier Tuning After the steady-state (static) AVP has been set and the current sense network has been optimized the Error Amplifier must be tuned. Basically, the gain of the Error Amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the Error Amplifier’s feedback capacitor (CA1 in the Applications Diagram). The bandwidth of the control loop will vary directly with the gain of the error amplifier. If CA1 is too large the loop gain/bandwidth will be low, the COMP pin will slew too slowly, and the output voltage will overshoot as shown in Figure 38. On the other hand, if CA1 is too small the loop gain/bandwidth will be high, the COMP pin will slew very quickly and overshoot. Integrator “wind up” is the cause of the overshoot. In this case the output voltage will transition more slowly because COMP spikes upward as shown in Figure 39. Too much loop gain/bandwidth increase the risk of instability. In general, one should use the lowest loop gain/bandwidth as possible to achieve acceptable transient response - this will insure good stability. If CA1 is optimal the COMP pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in Figure 40. After the control loop is tuned to provide an acceptable transient response the steady- state voltage ripple on the COMP pin should be examined. When the converter is operating at full, steady-state load, the peak-to-peak voltage ripple on the COMP pin should be less than 20 mVpp as shown in Figure 41. Less than 10 mVpp is ideal. Excessive ripple on the COMP pin will contribute to output voltage jitter. 9. Current Limit Setting When the output of the current sense amplifier (CO1 or CO2 in the block diagram) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing, the ILIM pin voltage should be set based on the inductor’s maximum resistance (RLMAX). The design must consider NOTE: At full load the peak-to-peak voltage ripple on the COMP pin should be less than 20 mV for a well-tuned/stable controller. Higher COMP voltage ripple will contribute to output voltage jitter. Figure 41. COMP Ripple for a Stable System |
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