PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 10 of 17
tCLZ
Clock to Low-Z[12, 13, 14]
0
0
0
ns
tCHZ
Clock to High-Z[12, 13, 14]
3.5
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
3.5
ns
tOELZ
OE LOW to Output Low-Z[12, 13, 14]
0
0
0
ns
tOEHZ
OE HIGH to Output High-Z[12, 13, 14]
3.5
3.5
3.5
ns
Setup Times
tAS
Address Set-up Before CLK Rise
1.5
2.0
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
2.0
2.0
ns
tADVS
ADV Set-up Before CLK Rise
1.5
2.0
2.0
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.5
2.0
2.0
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
1.5
ns
tCES
Chip Enable Set-up
1.5
2.0
2.0
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
ns
tWEH
GW,BWE, BWX Hold After CLK Rise
0.5
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
ns
Switching Characteristics Over the Operating Range (continued)[11, 12, 13, 14, 15, 16]
Parameter
Description
133 MHz
117 MHz
100 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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