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V•I Chip Pre-Regulator Module

P048K048T24AL

Rev. 1.4

Page 9 of 15

PRELIMINARY

L

O

A

D

-In

PC

VC

TM

+In

-Out

+Out

VTM

+Out

-Out

K

Ro

+Out

–Out

+In

–In

VC

PC

TM

IL

VH

PR

NC

SG

SC

PRM-AL

OS

NC

CD

Factorized

K

K

Vin

0.4

μH

Output Voltage Setting with Adaptive Loop

voltage are:

93100

( V

L

• 0.8395 ) – 1

(1)

K

91238

+ 1

(2)

K = VTM transformation ratio

(available from appropriate VTM data sheet)

(available from appropriate VTM data sheet)

(actual current delivered to the load)

Output Voltage Trimming (optional)

After setting the output voltage from the procedure above the output

may be margined down (26Vf min) by a resistor from SC-SG using this

formula:

A low voltage source can be applied to the SC port to margin the load

voltage in proportion to the SC reference voltage.

An external capacitor can be added to the SC port as shown in Figure 14 to

control the output voltage slew rate for soft start.

Figure 14 — Adaptive Loop compensation with soft start using the SC port.

Nominal Vout

VTM

Range (Vdc)

K Factor

0.8 ↔

1.6

1/32

1.1 ↔

2.2

1/24

1.6 ↔

3.3

1/16

2.2 ↔

4.4

1/12

3.3 ↔

6.6

1/8

4.3 ↔

8.8

1/6

6.5 ↔

13.4

1/4

8.7 ↔

17.9

1/3

13.0 ↔

26.9

1/2

17.4 ↔

36.0

2/3

26.0 ↔

54.0

1

Table 2 — 048 input series VTM K factor selection guide

Application Information

V•I Chip Pre-Regulator Module