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CY7C1378B-166AC Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1378B-166AC
Description  9-Mbit (256K x 32) Pipelined SRAM with NoBL Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1378B-166AC Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY7C1378B
Document #: 38-05435 Rev. *A
Page 10 of 14
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16]
200 MHz
166 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Unit
tPOWER
VDD (typical) to the First Access[13]
1
1
ms
Clock
tCYC
Clock Cycle Time
5.0
6.0
ns
tCH
Clock HIGH
2.0
2.4
ns
tCL
Clock LOW
2.0
2.4
ns
Output Times
tCO
Data Output Valid after CLK Rise
3.2
3.5
ns
tDOH
Data Output Hold after CLK Rise
1.5
1.5
ns
tCLZ
Clock to Low-Z[14, 15, 16]
1.5
1.5
ns
tCHZ
Clock to High-Z[14, 15, 16]
1.5
3.2
1.5
3.5
ns
tOEV
OE LOW to Output Valid
3.2
3.5
ns
tOELZ
OE LOW to Output Low-Z[14, 15, 16]
0
0
ns
tOEHZ
OE HIGH to Output High-Z[14, 15, 16]
3.2
3.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
1.5
1.5
ns
tALS
ADV/LD Set-up before CLK Rise
1.5
1.5
ns
tWES
GW, BW[A:D] Set-up before CLK Rise
1.5
1.5
ns
tCENS
CEN Set-up before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-up before CLK Rise
1.5
1.5
ns
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
ns
tWEH
GW, BW[A:D] Hold after CLK Rise
0.5
0.5
ns
tCENH
CEN Hold after CLK Rise
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
12. Test conditions shown in (a), (b) and (c) of AC Test Loads.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.


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