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ICS9248-163 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS9248-163 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 14 page 5 ICS9248-163 Preliminary Product Preview Third party brands and names are the property of their respective owners. Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) T I B# N I PD W PN O I T P I R C S E D 7 t i B- X # 2 S F 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- X # 3 S F 3 t i B0 41 T U O _ M A R D S 2 t i B- X # ) # 8 4 _ 4 2 L E S ( 1 t i B4 4 , 3 41 h t o b ( e l b a n e 0 K L C U P C d n a " e u r T " . r i a p l a i t n e r e f f i d ) " y r a t n e m i l p m o C 0 t i B6 41 e l b a n e T K L C U P C Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable) T I B# N I PD W PN O I T P I R C S E D 7 t i B- X # 0 S F 6 t i B7 1 F _ K L C I C P 5 t i B- 1 ) d e v r e s e R ( 4 t i B3 11 4 K L C I C P 3 t i B2 11 3 K L C I C P 2 t i B1 11 2 K L C I C P 1 t i B0 11 1 K L C I C P 0 t i B8 1 0 K L C I C P Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. T I B# N I PD W PN O I T P I R C S E D 7 t i B8 21 7 M A R D S 6 t i B9 21 6 M A R D S 5 t i B1 31 5 M A R D S 4 t i B2 31 4 M A R D S 3 t i B4 31 3 M A R D S 2 t i B5 31 2 M A R D S 1 t i B7 31 1 M A R D S 0 t i B8 31 0 M A R D S Byte 4: SDRAM , Active/Inactive Register (1= enable, 0 = disable) T I B# N I PD W PN O I T P I R C S E D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- X # E D O M 3 t i B- X # 1 S F 2 t i B- 1 ) d e v r e s e R ( 1 t i B8 41 1 F E R 0 t i B2 1 0 F E R Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable) Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable) T I B# N I PD W PN O I T P I R C S E D 7 t i B- 0 ) e t o N ( d e v r e s e R 6 t i B- 0 ) e t o N ( d e v r e s e R 5 t i B- 0 ) e t o N ( d e v r e s e R 4 t i B- 0 ) e t o N ( d e v r e s e R 3 t i B- 0 ) e t o N ( d e v r e s e R 2 t i B- 1 ) e t o N ( d e v r e s e R 1 t i B- 1 ) e t o N ( d e v r e s e R 0 t i B- 0 ) e t o N ( d e v r e s e R Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable) Note: Dont write into this register, writing into this register can cause malfunction T I B# N I PD W PN O I T P I R C S E D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 1 ) d e v r e s e R ( 5 t i B6 21 z H M 8 4 4 t i B5 21 z H M 8 4 _ 4 2 3 t i B7 11 1 1 M A R D S 2 t i B8 11 0 1 M A R D S 1 t i B0 21 9 M A R D S 0 t i B1 21 8 M A R D S |
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