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IDTQS74FCT2841ATSO Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDTQS74FCT2841ATSO Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 6 page 2 INDUSTRIALTEMPERATURERANGE IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH SOIC/ QSOP TOP VIEW 2 3 1 VCC 20 19 18 15 16 23 22 24 21 17 Y2 Y4 Y3 Y6 Y5 Y1 Y7 Y8 13 14 LE Y9 Y0 D4 D5 D3 D7 D6 D1 D2 D8 9 10 5 6 7 4 8 11 12 GND OE D0 D9 PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current Max Sink Current/Pin 120 mA IIK Input Diode Current, VIN < 0 –20 mA IOK Output Diode Current, VOUT < 0 –50 mA ABSOLUTE MAXIMUM RATINGS(1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTES: 1. This parameter is measured at characterization but not tested. 2. Pins 1-11, 13. 3. Pins 15-22. 4. Pins 14, 23. PIN DESCRIPTION Pin Names I/O Description Dx I LatchDataInputs LE I Thelatchenableinput.Thelatchesaretransparentwhen LEisHIGH.InputdataislatchedontheHIGH-to-LOW transition. Y x O 3-StateLatchOutputs OE I Theoutputenablecontrol.WhenOEisLOW,theoutputs are enabled. When OE is HIGH, the outputs Yx are in high-impedance(off)state. Symbol Parameter(1) Conditions Typ. Max. Unit CIN(2) Input Capacitance VIN = 0V 4 — pF COUT(3) Output Capacitance VOUT = 0V 6 — pF COUT(4) Output Capacitance VOUT = 0V 4 — pF FUNCTION TABLE(1) Inputs Internal Outputs OE LE Dx Value Qx Yx Function H H L L Z High-Z H H H H Z High-Z H L X N C Z Latched(High-Z) L H L L L Transparent L H H H H Transparent L L X N C N C Latched NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care NC = No Change Z = High-Impedance LOGIC SYMBOL Dx LE OE DQ Yx LE 10 10 |
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