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TLC555M Datasheet(PDF) 1 Page - Texas Instruments |
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TLC555M Datasheet(HTML) 1 Page - Texas Instruments |
1 / 42 page R1 R S 1 THRES R R R TRIG 2 1 GND DISCH 7 3 OUT 6 VDD 8 5 CONT RESET 4 Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLC555 SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019 TLC555 LinCMOS™ Timer 1 1 Features 1 • Very low power consumption: – 1-mW typical at VDD = 5 V • Capable of operation in astable mode • CMOS output capable of swinging rail to rail • High output current capability – Sink: 100-mA typical – Source: 10-mA typical • Output fully compatible with CMOS, TTL, and MOS • Low supply current reduces spikes during output transitions • Single-supply operation from 2 V to 15 V • Functionally interchangeable with the NE555; has same pinout • ESD protection exceeds 2000 V per MIL-STD- 883C, method 3015.2 • Available in Q-temp automotive – High-reliability automotive applications – Configuration control and print support – Qualification to automotive standards 2 Applications • Precision timing • Pulse generation • Sequential timing • Time delay generation • Pulse width modulation • Pulse position modulation • Linear ramp generator 3 Description The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip- flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLC555C SOIC (8) 4.90 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm SOP (8) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm TLC555I SOIC (8) 4.90 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm TLC555M LCCC (20) 8.89 mm × 8.89 mm CDIP (8) 9.60 mm × 6.67 mm TLC555Q SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic |
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