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PMS232-D18 Datasheet(PDF) 48 Page - PADAUK Technology. |
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PMS232-D18 Datasheet(HTML) 48 Page - PADAUK Technology. |
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48 / 94 page  PMC232/PMS232 Series 12-bit ADC Enhanced FPPA TM 8-bit OTP Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 48 of 94 PDK-DS-PMx232_V104– Dec. 18, 2018 Example 3: tm2c = 0b0001_1010, Y=8MHz tm2b = 0b0011_1111, K=63 tm2s = 0b1_00_00000, S1=1, S2=0 frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125kHz duty of output = [(63+1) ÷ 64] × 100% = 100% Example 4: tm2c = 0b0001_1010, Y=8MHz tm2b = 0b0000_0000, K=0 tm2s = 0b1_00_00000, S1=1, S2=0 frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125kHz duty = [(0+1) ÷ 64] × 100% =1.5% 5-10. WatchDog Timer The watchdog timer (WDT) is a counter with clock coming from ILRC and there are four different timeout periods of watchdog timer can be chosen by setting the misc register, it is: 256 ILRC clocks period if register misc[1:0]=11 2048 ILRC clocks period if register misc[1:0]=00 (default) 4096 ILRC clocks period if register misc[1:0]=01 16384 ILRC clocks period if register misc[1:0]=10 The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user should reserve guard band for save operation. WDT can be cleared by power-on-reset or by command wdreset at any time. When WDT is timeout, PMC232/PMS232 will be reset to restart the program execution. The relative timing diagram of watchdog timer is shown as Fig. 13. VDD WD Time Out Program Execution tSBP Watch Dog Time Out Sequence VDD WD Time Out Program Execution tSBP Watch Dog Time Out Sequence Fig.13: Sequence of Watch Dog Time Out |
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Similar Description - PMS232-D18 |
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