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PMS234-K24 Datasheet(PDF) 76 Page - PADAUK Technology. |
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PMS234-K24 Datasheet(HTML) 76 Page - PADAUK Technology. |
76 / 107 page PMC234/PMS234 Series 12-bit ADC Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 76 of 107 PDK-DS-PMX234_V103 – Dec. 19, 2018 6-23. Port D Data Register (pd), IO address = 0x1a Bit Reset R/W Description 7 - 2 - - Reserved 1 - 0 - R/W Bit [1:0] of data register for Port D. 6-24. Port D Control Register (pdc), IO address = 0x1b Bit Reset R/W Description 7 - 2 - - Reserved 1 - 0 00 R/W Bit [1:0] of port D control register. This register is used to define input mode or output mode for each corresponding pin. 0 / 1: input / output 6-25. Port D Pull-up Register (pdph), IO address = 0x1c Bit Reset R/W Description 7- 2 - - Reserved 1 - 0 00 R/W Bit [1:0] of Port D pull-up register. This register is used to enable the internal pull-up device on each corresponding pin. 0 / 1 : disable / enable 6-26. ADC Control Register (adcc), IO address = 0x20 Bit Reset R/W Description 7 0 R/W Enable ADC function. 0/1: Disable/Enable. 6 - R/W ADC process control bit. Write “1” to start AD conversion, and the flag is cleared automatically when starting the AD conversion ; Read “1” to indicate the completion of AD conversion and “0” is in progressing. 5 - 2 0000 R/W Channel selector. These four bits are used to select input signal for AD conversion. 0000: PB0/AD0, 0001: PB1/AD1, 0010: PB2/AD2, 0011: PB3/AD3, 0100: PB4/AD4, 0101: PB5/AD5, 0110: PB6/AD6, 0111: PB7/AD7 1000: PA3/AD8 1001: PA4/AD9 1111: band-gap 1.20 volt reference voltage Others: reserved 1 - 0 - - Reserved. (keep 0 for future compatibility) |
Similar Part No. - PMS234-K24 |
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Similar Description - PMS234-K24 |
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