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PMS234-D20 Datasheet(PDF) 79 Page - PADAUK Technology. |
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PMS234-D20 Datasheet(HTML) 79 Page - PADAUK Technology. |
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79 / 107 page  PMC234/PMS234 Series 12-bit ADC Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 79 of 107 PDK-DS-PMX234_V103 – Dec. 19, 2018 6-31. Timer2 Control Register (tm2c), IO address = 0x3c Bit Reset R/W Description 7 - 4 0000 R/W Timer2 clock selection. 0000 : disable 0001 : system clock 0010 : internal high RC oscillator (IHRC) 0011 : reserved 0100 : ILRC 0101 : comparator output 011x : reserved 1000 : PA0 (rising edge) 1001 : ~PA0 (falling edge) 1010 : PA3 (rising edge) 1011 : ~PA3 (falling edge) 1100 : PA4 (rising edge) 1101 : ~PA4 (falling edge) Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does NOT be stopped, Timer2 will keep counting when ICE is in halt state. 3 - 2 00 R/W Timer2 output selection. 00 : disable 01 : PA2 10 : PA3 11 : PA1 1 0 R/W Timer2 mode selection. 0 / 1 : period mode / PWM mode 0 0 R/W Enable to inverse the polarity of Timer2 output. 0 / 1: disable / enable. 6-32. Timer2 Counter Register (tm2ct), IO address = 0x3d Bit Reset R/W Description 7 - 0 0x00 R/W Bit [7:0] of Timer2 counter register. 6-33. Timer2 Scalar Register (tm2s), IO address = 0x37 Bit Reset R/W Description 7 0 WO PWM resolution selection. 0 : 8-bit 1 : 6-bit 6 - 5 00 WO Timer2 clock pre-scalar. 00 : ÷ 1 01 : ÷ 4 10 : ÷ 16 11 : ÷ 64 4 - 0 00000 WO Timer2 clock scalar. |
Similar Part No. - PMS234-D20 |
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Similar Description - PMS234-D20 |
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