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PMS234-S28 Datasheet(PDF) 67 Page - PADAUK Technology. |
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PMS234-S28 Datasheet(HTML) 67 Page - PADAUK Technology. |
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67 / 107 page  PMC234/PMS234 Series 12-bit ADC Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 67 of 107 PDK-DS-PMX234_V103 – Dec. 19, 2018 (2) Configure interrupt for ADC: (if desired) Clear the ADC interrupt request flag in bit 3 of intrq register Enable the ADC interrupt request in bit 3 of inten register Enable global interrupt by issuing engint command (3) Start AD conversion: Set ADC process control bit in the adcc register to start the conversion (set1 adcc.6). (4) Wait for the completion flag of AD conversion, by either: Waiting for the completion flag by using command “wait1 addc.6”; or Waiting for the ADC interrupt. (5) Read the ADC result registers: Read adcrh and adcrl the result registers (6) For next conversion, goto step 1 or step 2 as required. 5-17-1. The input requirement for AD conversion For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage reference high level and discharge to the voltage reference low level. The analog input model is shown as Fig. 25, the signal driving source impedance (Rs) and the internal sampling switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The internal sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will affect accuracy of analog input signal. User must ensure the measured signal is stable before sampling; therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to be measured. Fig. 25: Analog Input Model Before starting the AD conversion, the minimum signal acquisition time should be met for the selected analog input signal. The signal acquisition time (TACQ) of ADC in PMC234/PMS234 series is fixed to one clock period of ADCLK, the selection of ADCLK must be met the minimum signal acquisition time. |
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