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PMS271 Datasheet(PDF) 62 Page - PADAUK Technology. |
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PMS271 Datasheet(HTML) 62 Page - PADAUK Technology. |
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62 / 90 page  PMC271/PMS271 Series 8-bit ADC FPPA TM 8-bit Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 62 of 90 PDK-DS-PMX271-EN_V105 – Dec. 18, 2018 6.24. RESET Status Register (rstst), IO address = 0x25 Bit Reset (POR only) R/W Description 7 - 4 - - Reserved. Please don’t use.. 3 - R/W MCU reset from external reset pin (PA5)? This bit is set to high whenever reset occurs from PA5 pin, and reset only when writing “0” to clear this bit or POR (power-on-reset) happens. 0 / 1 : No / Yes. 2 - R/W VDD had been lower than 4V? This bit is set to high whenever VDD under 4V and reset only when writing “0” to clear this bit or POR (power-on-reset) happens. 0 / 1 : No / Yes. 1 - R/W VDD had been lower than 3V? This bit is set to high whenever VDD under 3V and reset only when writing “0” to clear this bit or POR (power-on-reset) happens. 0 / 1 : No / Yes. 0 - R/W VDD had been lower than 2V? This bit is set to high whenever VDD under 2V and reset only when writing “0” to clear this bit or POR (power-on-reset) happens. 0 / 1 : No / Yes. 6.25. MISC Register (misc), IO address = 0x3b Bit Reset R/W Description 7 0 - Reserved 6 0 WO Enable extremely low current for 32KHz crystal oscillator AFTER oscillation. 0: Normal. 1: Low driving current for 32KHz crystal oscillator. 5 0 WO Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled. 0: Normal wake-up. The wake-up time is 1024 ILRC clocks 1: Fast wake-up. (for The wake-up time is 128 CLKs (system clock) + oscillator stable time. If wake-up from STOPEXE suspend, there is no oscillator stable time; If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from power-on. Please notice that the clock source will be switched to system clock (for example: 4MHz) when fast wakeup is enabled, therefore, it is recommended to turn off the watchdog timer before enabling the fast wakeup and turn on the watchdog timer after disabling the fast wakeup. 4 0 WO Enable to generate half VDD on PA0/PA1/PA2/PA3 pins. 0 / 1 : Disable / Enable 3 0 WO Recover time from LVR reset. 0: Normal. The system will take about 1024 ILRC clocks to boot up from LVR reset. 1: Fast. The system will take about 64 ILRC clocks to boot up from LVR reset. 2 0 WO Disable LVR function.0 / 1 : Enable / Disable 1 - 0 00 WO Watch dog time out period 00: 2048 ILRC clock period 01: 4096 ILRC clock period 10: 16384 ILRC clock period 11: 256 ILRC clock period |
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