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ASM5I9774A-52-ER Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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ASM5I9774A-52-ER Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
7 / 12 page June 2005 ASM5I9774A rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 7 of 12 Notice: The information in this document is subject to change without notice. AC Electrical Specifications (VDD = 2.5V ± 5%, T A = –40°C to +85°C) 1 Parameter Description Condition Min Typ Max Unit f VCO VCO Frequency 200 - 400 MHz ÷8 Feedback 25 - 50 ÷12 Feedback 16.6 - 33.3 ÷16 Feedback 12.5 - 25 ÷24 Feedback 8.3 - 16.6 ÷32 Feedback 6.3 - 12.5 ÷48 Feedback 4.2 - 8.3 f in Input Frequency Bypass mode (PLL_EN = 0) 0 - 200 MHz f refDC Input Duty Cycle 25 - 75 % t r, tf TCLK Input Rise/FallTime 0.7V to 1.7V – - 1.0 nS ÷4 Output 50 - 100 ÷8 Output 25 - 50 ÷12 Output 16.6 - 33.3 ÷16 Output 12.5 - 25 f MAX Maximum Output Frequency ÷24 Output 8.3 - 16.6 MHz DC Output Duty Cycle 45 - 55 % t r, tf Output Rise/Fall times 0.7V to 1.8V 0.1 - 0.75 nS t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, does not include jitter –100 - 100 pS t sk(O) Output-to-Output Skew Skew within Bank - - 150 pS Banks at same frequency - - 150 tsk(B) Bank-to-Bank Skew Banks at different frequency - - 200 pS t PLZ, HZ Output Disable Time - - 10 nS t PZL, ZH Output Enable Time - - 10 nS BW PLL Closed Loop Bandwidth (–3 dB) - 0.5 -1.0 - MHz Same frequency - - 100 t JIT(CC) Cycle-to-Cycle Jitter Multiple frequencies - - 250 pS t JIT(PER) Period Jitter - - 100 pS t JIT(φ) I/O Phase Jitter - - 125 pS t LOCK Maximum PLL Lock Time - - 1 mS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. |
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