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ASM5I9772AG-52-ER Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation |
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ASM5I9772AG-52-ER Datasheet(HTML) 10 Page - Alliance Semiconductor Corporation |
10 / 15 page June 2005 ASM5I9772A rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 10 of 15 Notice: The information in this document is subject to change without notice. Power Management The individual output enable / freeze control of the ASM5I9772A allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs cannot be frozen with the serial port. This avoids any potential lock up situation should an error occur in the loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode VCO QA QC SYNC QA QC SYNC QA QC SYNC QA QC SYNC QA QC SYNC QA QC SYNC QA QC SYNC Figure 1 |
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