June 2005

ASM5I9773A

rev 0. 3

2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer

2 of 16

Notice: The information in this document is subject to change without notice.

Block Diagram

Pin Configuration

AVSS

MR#/OE

SCLK

FB_SEL2

PLL_EN

REF_SEL

TCLK_SEL

TCLK0

TCLK1

PECL_CLK

SDATA

FB_IN

QB3

VDDQB

QB2

VSS

QB1

VDDQB

QB0

VSS

VSS

FB_OUT

1

2

4

3

5

6

7

8

9

10

11

52 51 50 49 48 47 46 45 44

41 40

14 15 16 17 18 19 20 21 22 23 24

39

38

37

36

35

34

33

32

31

30

29

ASM5I9773A

12

13

25 26

27

28

43 42

PECL_CLK#

AVDD

VDD

FB_SEL0

Sync

Frz

Sync

Frz

Sync

Frz

Sync

Frz

Sync

Frz

Sync

Frz

D Q

D Q

D Q

D Q

D Q

D Q

D Q

0

1

/2

Output Disable

Circuitry

12

Power-On

Reset

0

1

VCO

Phase

Detector

LPF

0

1

/4,/6,/8,/12

/4,/6,/8,/10

/2,/4,/6,/8

/4,/6,/8,/10

Sync Pulse

Data Generator

2

2

2

2

PECL_CLK

PECL_CLK#

VCO_SEL

PLL_EN

REF_SEL

TCLK0

TCLK1

TCLK_SEL

FB_IN

FB_SEL2

MR#/OE

SELA(0,1)

SELB(0,1)

SELC(0,1)

FB_SEL(0,1)

SCLK

SDATA

INV_CLK

SYNC

FB_OUT

QC3

QC2

QC1

QC0

QB3

QB2

QB1

QB0

QA3

QA2

QA1

QA0