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ASM5I9653A Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation |
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ASM5I9653A Datasheet(HTML) 8 Page - Alliance Semiconductor Corporation |
8 / 13 page July 2005 ASM5I9653A rev 0.2 3.3V 1:8 LVCMOS PLL Clock Generator 8 of 13 Notice: The information in this document is subject to change without notice. Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 .Single versus Dual Line Termination Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the ASM5I9653A output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the ASM5I9653A. The output waveform in Figure 7 Single versus Dual Line Termination Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0 = 50Ω || 50Ω RS = 36 Ω || 36 Ω R0 = 14 Ω VL = 3.0 ( 25 ⎟ (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8 .Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. 14 Ω + 22Ω _ 22Ω = 50Ω _ 50Ω 25 Ω = 25Ω Figure 8. Optimized Dual Line Termination ASM5I9653A OUTPUT BUFFER 14Ω IN OUTA Z0=15Ω RS=36Ω ASM5I9653A OUTPUT BUFFER 14Ω IN OUTB1 Z0=15Ω RS=36Ω OUTB0 Z0=15Ω RS=36Ω ASM5I9653A OUTPUT BUFFER 14Ω IN Z0=15Ω RS=22Ω Z0=15Ω RS=22Ω |
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