R1LV1616R Series

Rev.1.00

2004.04.13

page 9 of 16

Write Cycle

Note

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. AT any given temperature and voltage condition,

form device to device.

4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#

going low or UB# going low .

A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#

going high or UB# going high.

5.

6.

7.

1,2

ns

30

0

25

0

Write to output in high-Z

Write pulse width

1,2

ns

30

0

25

0

Output disable to output in high-Z

2

ns

-

5

-

5

Output active from end of write

ns

-

0

-

0

Data hold from write time

ns

-

40

-

35

Data to write time overlap

7

ns

-

0

-

0

Write recovery time

6

ns

-

0

-

0

Address setup time

ns

-

70

-

65

LB#,UB# valid to end of write

4

ns

-

60

-

55

5

ns

-

70

-

65

Chip selection to end of write

ns

-

70

-

65

Address valid to end of write

ns

-

85

-

70

Write cycle time

Max.

Min.

Max.

Min.

Notes

Unit

R1LV1616R**-8S

R1LV1616R**-7S

Symbol

Parameter