July 2005

ASM5I961C

rev 0.2

Alliance Semiconductor

2575 Augustine Drive

• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

Low Voltage Zero Delay Buffer

Features

Fully Integrated PLL

Up to 200MHz I/O Frequency

LVCMOS Outputs

Outputs Disable in High Impedance

LVCMOS Reference Clock Options

LQFP and TQFP Packaging

±50pS Cycle–Cycle Jitter

150pS Output Skews

Functional Description

The ASM5I961C is a 2.5V or 3.3V compatible, 1:18 PLL

based zero delay buffer. With output frequencies of up to

200MHz, output skews of 150pS the device meets the

needs of the most demanding clock tree applications.

The ASM5I961 is offered with two different input

configurations. The ASM5I961C offers an LVCMOS

reference clock while the ASM5I961P offers an LVPECL

reference clock.

When pulled high the OE pin will force all of the outputs

(except QFB) into a high impedance state. Because the OE

pin does not affect the QFB output, down stream clocks

can be disabled without the internal PLL losing lock.

The ASM5I961C is fully 2.5V or 3.3V compatible and

requires no external loop filter components. All control

inputs accept LVCMOS compatible levels and the outputs

provide low impedance LVCMOS outputs capable of

driving terminated 50Ω transmission lines. For series

terminated lines the ASM5I961C can drive two lines per

output giving the device an effective fanout of 1:36. The

device is packaged in a 32 lead LQFP and TQFP

Packages.

Block Diagram

Figure 1. ASM5I961C Logic Diagram

Q0

Q1

Q2

Q3

Q14

Q15

Q16

QFB

0

1

100-200 MHz

50-100 MHz

Ref

FB

PLL

50K

50K

50K

50K

CCLK

FB_IN

F_RANGE

OE