July 2005

ASM5I961P

rev 0.2

Low Voltage Zero Delay Buffer

7 of 14

Notice: The information in this document is subject to change without notice.

a step in the waveform, this step is caused by the

impedance mismatch seen looking into the driver. The

parallel combination of the 36

Ω series resistor plus the

output

impedance

does

not

match

the

parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50

Ω || 50Ω

Rs = 36

Ω || 36Ω

Ro = 14

Ω

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.62V. It will then increment

towards the quiescent 3.0V in steps separated by one

round trip delay (in this case 4.0nS).

Figure 5. Single versus Dual Waveforms

Since this step is well above the threshold region it will

not cause any false clock triggering, however designers

may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving

multiple lines the situation in Figure 6. should be used. In

this case the series terminating resistors are reduced

such that when the parallel combination is added to the

output buffer impedance the line impedance is perfectly

matched.

14

Ω + 22Ω || 22Ω = 50Ω || 50Ω

25

Ω = 25Ω

Figure 6. Optimized Dual Line Termination

Using the ASM5I961P in zero-delay applications

Nested clock trees are typical applications for the

ASM5I961P. Designs using the ASM5I961P, as LVCMOS

PLL fanout buffer with zero insertion delay will show

significantly lower clock skew than clock distributions

developed from CMOS fanout buffers. The external

feedback option of the ASM5I961P clock driver allows for

its use as a zero delay buffer. By using the QFB output as

a feedback to the PLL the propagation delay through the

device is virtually eliminated. The PLL aligns the

feedback clock output edge with the clock input reference

edge resulting a near zero delay through the device. The

maximum insertion delay of the device in zero-delay

applications is measured between the reference clock

input and any output. This effective delay consists of the

static phase offset, I/O jitter (phase or long-term jitter),

feedback path delay and the output-to-output skew error

relative to the feedback output.

Calculation of part-to-part skew

The ASM5I961P zero delay buffer supports applications

where critical clock signal timing can be maintained

across several devices. If the reference clock inputs of

two or more ASM5I961P are connected together, the

maximum overall timing uncertainty from the common

PCLK input to any output is:

This

maximum

timing

uncertainty

consist

of

4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

Figure 7. ASM5I961P max. device-to-device skew

Due to the statistical nature of I/O jitter a rms value (1

σ) is

specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

ASM5I961P

OUTPUT BUFFER

14Ω

IN

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

TIME (nS)

In

OutA

OutB

Max. skew