July 2005

ASM5I961P

rev 0.2

Low Voltage Zero Delay Buffer

11 of 14

Notice: The information in this document is subject to change without notice.

The time from the PLL controlled edge to the

non-controlled edge, divided by the time

between PLL controlled edges, expressed as a

percentage.

GND

Figure 14. Output Duty Cycle (DC)

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation delay between any similar

delay path within a single device

test reference

PCLK

GND

PCLK

Ext_FB

Figure 16. Cycle-to-cycle Jitter

The variation in cycle time of a signal between adjacent

cycles, over a random sample of adjacent cycle pairs

Figure 17. Period Jitter

The deviation in cycle time of a signal with respect to the

ideal period over a random sample of cycles

VCC = 3.3V VCC = 2.5V

2.4

1.8V

0.55

0.6V

Figure 13. Output Transition Time Test Reference

PCLK

Ext_FB

in a random sample of cycles

Figure 18.I/O Jitter

PCLK