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HL7548 Datasheet(PDF) 39 Page - List of Unclassifed Manufacturers

Part No. HL7548
Description  Product Technical Specification
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HL7548 Datasheet(HTML) 39 Page - List of Unclassifed Manufacturers

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4116369
Rev 9.0
September 04, 2017
39
5. Design Guidelines
5.1. Power-Up Sequence
Apply a low-level logic to the PWR_ON_N pad (pad 59); within approximately 25ms, VGPIO will
appear to be at 1.8V. Either UART1 or the USB interface could be used to send AT commands. The
AT command interface is available in about 7 seconds after PWR_ON_N for either UART1 or USB.
When using UART1, the AT command interface is available after the transition of UART1_CTS from
high to low level.
When using a USB connection, the HL7548 and HL7588 will start communicating with the host after
USB enumeration. The time when AT commands can be sent will depend on the initialization time on
the USB host.
Module is ON
Module is OFF
2000 ms
<25 ms
7 secs
Module is ready to receive AT
commands via UART1
Signal level depends on
Hardware Flow Control settings
PWR_ON_N
VGPIO
UART1_CTS
Figure 8.
PWR_ON_N Sequence with VGPIO Information
Note:
As PWR_ON_N is internally pulled up with 100kΩ, an open collector or open drain transistor must
be used for ignition.
The PWR_ON_N pad has the minimum assertion time requirement of 25ms, with LOW active. Once
the valid power on trigger is detected, the PWR_ON_N pad status can be left open.
The maximum inrush current is 1.3 A and lasts less than 1.5 ms.


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