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PM49FL004T-33JCE Datasheet(PDF) 8 Page - PMC-Sierra, Inc |
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PM49FL004T-33JCE Datasheet(HTML) 8 Page - PMC-Sierra, Inc |
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8 / 46 page  Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4 PMC Pm49FL002 / 004 8 SECTOR AND BLOCK ERASE The Pm49FL002 contains sixty-four uniform 4 Kbyte sec- tors, or sixteen uniform 16 Kbyte blocks (sector group - consists of four adjecent sectors). The Pm49FL004 con- tains one hundred and twenty-eight uniform 4 Kbyte sec- tors, or eight uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). A sector erase command is used to erase an individual sector. A block erase command is used to erase an individual block. See Table 12 - 13 for Sector/Block Address Tables. In FWH/LPC mode, an erase operation is activated by writing the six-byte command sequence through six con- secutive write memory cycles. In A/A Mux mode, an erase operation is activated by writing the six-byte com- mand in six consecutive bus cycles. Pre-programs the sector or block is not required prior to an erase opera- tion. I/O7 DATA# POLLING The devices provide a Data# Polling feature to indicate the progress or the completion of a program or erase operation in all modes. During a program operation, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is complete, the true data of the last loaded data is valid on all outputs. During an erase operation, an attempt to read the device will result a “0” on I/O7. After the erase cycle is complete, an attempt to read the device will result a “1” on I/O7. DEVICE OPERATION (CONTINUED) I/O6 TOGGLE BIT The Pm49FL002/004 also provide a Toggle Bit feature to detect the progress or the completion of a program or erase operation. During a program or erase operation, an attempt to read data from the devices will result in I/ O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase operation. RESET Any read, program, or erase operation to the devices can be reset by the INIT# or RST# pins. INIT# and RST# pins are internally hard-wired and have same function to the devices. The INIT# pin is only available in FWH and LPC modes. The RST# pin is available in all modes. It is required to drive INIT# or RST# pins low during sys- tem reset to ensure proper initialization. During a memory read operation, pulls low the INIT# or RST# pin will reset the devices back to standby mode and then the FWH[3:0] of FWH interface or the LAD[3:0] of LPC interface will go to high impedance state. During a program or erase operation, pulls low the INIT# or RST# pin will abort the program or erase operation and reset the devices back to standby mode. A reset latency will occur before the devices resume to standby mode when such reset is performed. When a program or erase op- eration is reset before the completion of such opera- tion, the memory contents of devices may become invalid due to an incomplete program or erase opera- tion. |
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