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AS7C33512NTF18A Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

Part No. AS7C33512NTF18A
Description  3.3V 512K x 18 Flowthrough Synchronous SRAM with NTD
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Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
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AS7C33512NTF18A Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation

 
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®
AS7C33512NTF18A
11/8/04, v. 1.1
Alliance Semiconductor
P. 4 of 18
Functional description
The AS7C33512NTF18A family is a high performance CMOS 8 Mbit Synchronous Static Random Access Memory (Flowthrough SRAM)
organized as 524,288 words × 18 bits and incorporates a LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal flowthrough burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for
valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or read-
modify-write operations.
NTDdevices use the memory bus more efficiently by introducing a write latency that matches one-cycle flow-through read latency. Write
data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD, write and read operations
can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock
cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,
R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,
including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTF18A operates with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate power supply
(VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package
*Guaranteed not tested
TQFP thermal resistance
Capacitance
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
CIN*
Vin = 0V
-
5
pF
I/O capacitance
CI/O*
Vin = Vout = 0V
-
7
pF
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
θJA
40
°C/W
4–layer
θJA
22
°C/W
Thermal resistance
(junction to top of case)1
θJC
8
°C/W


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