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AS7C33512NTF18A Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

Part No. AS7C33512NTF18A
Description  3.3V 512K x 18 Flowthrough Synchronous SRAM with NTD
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Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
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AS7C33512NTF18A Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation

 
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November 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33512NTF18A
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
3.3V 512K×18 Flowthrough Synchronous SRAM with NTDTM
Features
• Organization: 524,288 words × 18 bits
•NTDarchitecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic Block Diagram
Selection Guide
-75
-85
-10
Units
Minimum cycle time
8.5
10
12
ns
Maximum clock access time
7.5
8.5
10
ns
Maximum operating current
280
260
220
mA
Maximum standby current
120
110
100
mA
Maximum CMOS standby current (DC)
30
30
30
mA
Address
D
Q
CLK
register
Output
buffer
DQ [a,b]
19
19
CLK
CE0
CE1
CE2
A[18:0]
OE
CEN
Control
CLK
logic
Data
D
Q
CLK
input
register
18
18
OE
512K x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
Q
D
FT
ADV / LD
LBO
burst logic
addr. registers
Write delay
19
ZZ
CLK
18
18
18
18


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