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AS7C33512NTD18A Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

Part # AS7C33512NTD18A
Description  3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C33512NTD18A Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation

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November 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33512NTD18A
3.3V 512K
× 18 Pipelined burst Synchronous SRAM with NTDTM
11/30/04; v.2.1
Alliance Semiconductor
1 of 19
Features
• Organization: 524,288 words × 18 bits
•NTD™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed WRITE cycles
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
Selection Guide
-166
–133
Units
Minimum cycle time
6
7.5
ns
Maximum clock frequency
166
133
MHz
Maximum clock access time
3.5
4
ns
Maximum operating current
475
400
mA
Maximum standby current
130
100
mA
Maximum CMOS standby current (DC)
30
30
mA
Address
D
Q
CLK
register
Output
Register
DQ[a:b]
18
18
19
19
CLK
CE0
CE1
CE2
A[18:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
18
18
OE
512K x 18
SRAM
Array
R/W
DQ [a:b]
BWa
BWb
CLK
Q
D
ADV/LD
LBO
Burst logic
addr. registers
Write delay
18
19
Logic block diagram
ZZ
18
CLK


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