Device

IN

OUT

GND

Schottky Diode

Internal Body Diode

23

TPS745-Q1

www.ti.com

SBVS355A – JUNE 2019 – REVISED OCTOBER 2019

Product Folder Links: TPS745-Q1

Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

Application Information (continued)

If reverse current flow is expected in the application, external protection must be used to protect the device.

Figure 57 shows one approach of protecting the device.

Figure 57. Example Circuit for Reverse Current Protection Using a Schottky Diode

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit

board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no

other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

(4)

NOTE

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by

correct selection of the system voltage rails. For the lowest power dissipation use the

minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-

(5)

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm printed circuit board (PCB) of two and four layers.

For the four-layer board, the inner planes use a 1-oz copper thickness. Outer layers are simulated with both 1-oz

and 2-oz copper thickness. A 2 x 1 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located

beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case

of the 4-layer board, the first inner GND plane.