9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

In this application, the SN74HCS595 is used to control seven-segment displays. Utilizing the serial output and

combining a few of the input signals, this implementation reduces the number of I/O pins required to control the

displays from sixteen to four. Unlike other I/O expanders, the SN74HCS595 does not need a communication

interface for control. It can be easily operated with simple GPIO pins.

The OE pin is used to easily disable the outputs when the displays need to be turned off or connected to a PWM

signal to control brightness. However, this pin can be tied low and the outputs of the SN74HCS595 can be

controlled accordingly to turn off all the outputs reducing the I/O needed to three. There is no practical limitation

to how many SN74HCS595 devices can be cascaded. To add more, the serial output will need to be connected

to the following serial input and the clocks will need to be connected accordingly. With separate control for the

shift registers and output registers, the desired digit can be displayed while the data for the next digit is loaded

into the shift register.

At power-up, the initial state of the shift registers and output registers are unknown. To give them a defined state,

the shift register needs to be cleared and then clocked into the output register. An RC can be connected to the

SRCLR pin as shown in the Typical application block diagram to initialize the shift register to all zeros. With the

OE pin pulled up with a resistor, this process can be performed while the outputs are in a high impedance state

eliminating any erroneous data causing issues with the displays.

9.2 Typical Application

Seven Segment

SRCLR

g

f

a

b

DP

c

d

e

a

b

c

d

e

f

g

DP

GND

SER

SRCLK

RCLK

OE

SRCLR

GND

SER

SRCLK

RCLK

OE

Seven Segment

g

f

a

b

DP

c

d

e

a

b

c

d

e

f

g

DP

MCU

R2

C2

R1

C1

Figure 9-1. Typical application block diagram

SN74HCS595

SCLS803 – AUGUST 2020

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