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DRV8889-Q1 Datasheet(PDF) 47 Page - Texas Instruments

Part No. DRV8889-Q1
Description  DRV8889-Q1, DRV8889A-Q1 Automotive Stepper Driver with Integrated Current Sense, 1/256 Micro-Stepping, and Stall Detection
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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DRV8889-Q1 Datasheet(HTML) 47 Page - Texas Instruments

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Table 7-21. DIAG Status 1 Register Field Descriptions
Bit
Field
Type
Default
Description
7
OCP_LS2_B
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 2
in BOUT
6
OCP_HS2_B
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 2
in BOUT
5
OCP_LS1_B
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 1
in BOUT
4
OCP_HS1_B
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 1
in BOUT
3
OCP_LS2_A
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 2
in AOUT
2
OCP_HS2_A
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 2
in AOUT
1
OCP_LS1_A
R
0b
Indicates overcurrent fault on the low-side FET of half bridge 1
in AOUT
0
OCP_HS1_A
R
0b
Indicates overcurrent fault on the high-side FET of half bridge 1
in AOUT
7.6.4 DIAG Status 2 (address = 0x02)
DIAG Status 2 is shown in Figure 7-35 and described in Table 7-22.
Read-only
Figure 7-35. DIAG Status 2 Register
7
6
5
4
3
2
1
0
UTW
OTW
OTS
STL_LRN_OK
STALL
RSVD
OL_B
OL_A
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 7-22. DIAG Status 2 Register Field Descriptions
Bit
Field
Type
Default
Description
7
UTW
R
0b
Indicates undertemperature warning.
6
OTW
R
0b
Indicates overtemperature warning.
5
OTS
R
0b
Indicates overtemperature shutdown.
4
STL_LRN_OK
R
0b
Indicates stall detection learning is successful
3
STALL
R
0b
Indicates motor stall condition
2
RSVD
R
0b
Reserved.
1
OL_B
R
0b
Indicates open-load detection on BOUT
0
OL_A
R
0b
Indicates open-load detection on AOUT
7.6.5 Control Registers
The IC control registers are used to configure the device. Status registers are read and write capable.
Table 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in
Table 7-23 should be considered as reserved locations and the register contents should not be modified.
www.ti.com
DRV8889-Q1
SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
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