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DRV8889-Q1 Datasheet(PDF) 38 Page - Texas Instruments

Part No. DRV8889-Q1
Description  DRV8889-Q1, DRV8889A-Q1 Automotive Stepper Driver with Integrated Current Sense, 1/256 Micro-Stepping, and Stall Detection
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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DRV8889-Q1 Datasheet(HTML) 38 Page - Texas Instruments

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Table 7-10. Fault Condition Summary (continued)
FAULT
CONDITION
CONFIGU
RATION
ERROR
REPORT
H-BRIDGE CHARGE
PUMP
INDEXER
LOGIC
RECOVERY
Open Load (OL)
No load detected
EN_OL =
1b
nFAULT /
SPI
Operating
Operating
Operating
Operating
Report only
Stall Detection
(STALL)
Stall / stuck motor
STL_REP
= 0b
SPI
Operating
Operating
Operating
Operating
CLR_FLT/ nSLEEP
STL_REP
= 1b
nFAULT /
SPI
Operating
Operating
Operating
Operating
Overtemperature
Warning (OTW)
TJ > TOTW
TW_REP =
1b
nFAULT /
SPI
Operating
Operating
Operating
Operating
Automatic: TJ <
TOTW - THYS_OTW
TW_REP =
0b
SPI
Operating
Operating
Operating
Operating
Undertemperature
Warning (UTW)
TJ < TUTW
TW_REP =
1b
nFAULT /
SPI
Operating
Operating
Operating
Operating
Automatic: TJ >
TUTW + THYS_UTW
TW_REP =
0b
SPI
Operating
Operating
Operating
Operating
Thermal Shutdown
(OTSD)
TJ > TOTSD
OTSD_MO
DE = 0b
nFAULT /
SPI
Disabled
Disabled
Operating
Operating
Latched:
CLR_FLT / nSLEEP
OTSD_MO
DE = 1b
SPI
Disabled
Disabled
Operating
Operating
Automatic: TJ <
TOTSD - THYS_OTSD
7.4 Device Functional Modes
7.4.1 Sleep Mode (nSLEEP = 0)
The device state is managed by the nSLEEP pin. When the nSLEEP pin is low, the device enters a low-power
sleep mode. In sleep mode, all the internal MOSFETs are disabled, the DVDD regulator is disabled, the charge
pump is disabled, and the SPI is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin
before the device enters sleep mode. The device is brought out of sleep automatically if the nSLEEP pin is
brought high. The tWAKE time must elapse before the device is ready for inputs.
7.4.2 Disable Mode (nSLEEP = 1, DRVOFF = 1)
The DRVOFF pin is used to enable or disable the half bridges in the device. When the DRVOFF pin is high, the
output drivers are disabled in the Hi-Z state.
The DIS_OUT bit can also be used to disable the output drivers. When the DIS_OUT bit is '1', the output drivers
are disabled in the Hi-Z state. DIS_OUT is OR'ed with DRVOFF pin.
Table 7-11. Conditions to Enable or Disable Output Drivers
nSLEEP
DRVOFF
DIS_OUT
H-BRIDGE
0
Don't Care
Don't Care
Disabled
1
0
0
Operating
1
0
1
Disabled
1
1
0
Disabled
1
1
1
Disabled
7.4.3 Operating Mode (nSLEEP = 1, DRVOFF = 0)
When the nSLEEP pin is high, the DRVOFF pin is low, and VM > UVLO, the device enters the active mode. The
tWAKE time must elapse before the device is ready for inputs.
7.4.4 nSLEEP Reset Pulse
In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared through a quick nSLEEP pulse.
This pulse width must be greater than 18 µs and shorter than 35 µs. If nSLEEP is low for longer than 35 µs but
less than 75 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing diagram
DRV8889-Q1
SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020
www.ti.com
38
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: DRV8889-Q1


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