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DRV8889-Q1 Datasheet(PDF) 37 Page - Texas Instruments

Part No. DRV8889-Q1
Description  DRV8889-Q1, DRV8889A-Q1 Automotive Stepper Driver with Integrated Current Sense, 1/256 Micro-Stepping, and Stall Detection
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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DRV8889-Q1 Datasheet(HTML) 37 Page - Texas Instruments

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Stall threshold can be set in two ways – either user can write the STALL_TH bits, or let the algorithm learn the
stall threshold value itself through the stall learning process. The stall learning process requires that the
STL_LRN bit in CTRL5 register is '1' and the motor is deliberately stalled for some time to allow the algorithm to
learn the ideal stall threshold. The process takes 16 electrical cycles and at the end of a successful learning,
loads the STALL_TH register with the proper stall threshold bits. Also, the STL_LRN_OK bit goes high at the end
of successful learning. It is recommended that users set the stall threshold using the stall learning process for
proper stall detection. A stall threshold at one speed may not work well for another speed - therefore it is
recommended to re-learn the stall threshold when the motor speed changes.
7.3.11.6 Thermal Shutdown (OTSD)
If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled,
and the nFAULT pin is driven low. The charge pump is disabled in this condition. In addition, the FAULT, TF and
OTS bits are latched high. This protection feature cannot be disabled. The overtemperature protection can
operate in two different modes: latched shutdown and automatic recovery.
7.3.11.6.1 Latched Shutdown (OTSD_MODE = 0b)
In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF
and OTS bits are latched high in the SPI register. Normal operation resumes after sending a CLR_FLT
command, or an nSLEEP reset pulse or a power cycling. This mode is the default mode for a OTSD event.
7.3.11.6.2 Automatic Recovery (OTSD_MODE = 1b)
In this mode, after a OTSD event all the outputs are disabled and the nFAULT pin is driven low. The FAULT, TF
and OTS bits are latched high in the SPI register. Normal operation resumes (motor-driver operation starts,
nFAULT line released and FAULT bit goes low) when the junction temperature falls below the overtemperature
threshold limit minus the hysteresis (TOTSD – THYS_OTSD). The TF and OTS bits remains latched high indicating
that a thermal event occurred until a clear faults command is issued either through the CLR_FLT bit or an
nSLEEP reset pulse.
7.3.11.7 Overtemperature Warning (OTW)
If the die temperature exceeds the trip point of the overtemperature warning (TOTW), the OTW and TF bits are
set in the SPI register. The device performs no additional action and continues to function. When the die
temperature falls below the hysteresis point (THYS_OTW) of the overtemperature warning, the OTW and TF bits
clear automatically. The OTW bit can also be configured to report on the nFAULT pin, and set the FAULT bit in
the device, by setting the TW_REP bit to 1b through the SPI registers. The charge pump remains active during
this condition.
7.3.11.8 Undertemperature Warning (UTW)
If the die temperature falls below the trip point of the undertemperature warning (TUTW), the UTW and TF bits are
set in the SPI register. The device performs no additional action and continues to function. When the die
temperature exceeds the hysteresis point (THYS_UTW) of the undertemperature warning, the UTW and TF bits
clear automatically. The UTW bit can also be configured to report on the nFAULT pin, and set the FAULT bit in
the device, by setting the TW_REP bit to 1b through the SPI registers. The charge pump remains active during
this condition.
Table 7-10. Fault Condition Summary
FAULT
CONDITION
CONFIGU
RATION
ERROR
REPORT
H-BRIDGE CHARGE
PUMP
INDEXER
LOGIC
RECOVERY
VM undervoltage
(UVLO)
VM < VUVLO
(max 4.35 V)
nFAULT /
SPI
Disabled
Disabled
Disabled
Reset
(VVM < 3.9
V)
Automatic: VM >
VUVLO
(max 4.45 V)
VCP undervoltage
(CPUV)
VCP < VCPUV
(typ VM + 2.25 V)
nFAULT /
SPI
Disabled
Operating
Operating
Operating
VCP > VCPUV
(typ VM + 2.7 V)
Overcurrent (OCP)
IOUT > IOCP
(min 2.4 A)
OCP_MOD
E = 0b
nFAULT /
SPI
Disabled
Operating
Operating
Operating
Latched:
CLR_FLT / nSLEEP
OCP_MOD
E = 1b
nFAULT /
SPI
Disabled
Operating
Operating
Operating
Automatic retry:
tRETRY
www.ti.com
DRV8889-Q1
SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
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