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DRV8889-Q1 Datasheet(PDF) 36 Page - Texas Instruments

Part No. DRV8889-Q1
Description  DRV8889-Q1, DRV8889A-Q1 Automotive Stepper Driver with Integrated Current Sense, 1/256 Micro-Stepping, and Stall Detection
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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DRV8889-Q1 Datasheet(HTML) 36 Page - Texas Instruments

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between rising and falling current quadrants of the motor current, the device can detect a motor overload stall
condition or an end-of-line travel.
Figure 7-21. Stall Detection by Monitoring Motor Back-EMF
The Stall Detection algorithm works only when the device is programmed to operate in the smart tune Ripple
Control decay mode. The EN_STL bit in CTRL5 register has to be '1' to enable stall detection. The algorithm
compares the back-EMF between the rising and falling current quadrants by monitoring PWM off time and
generates a value represented by the 8-bit register TRQ_COUNT. The comparison is done in such a way that
the TRQ_COUNT value is practically independent of motor current, motor winding resistance, ambient
temperature and supply voltage. Full step mode of operation is supported by this algorithm.
For a lightly loaded motor, the TRQ_COUNT will be a non-zero value. As the motor approaches stall condition,
TRQ_COUNT will approach zero and can be used to detect stall condition. If anytime TRQ_COUNT falls below
the stall threshold (represented by the 8-bit STALL_TH register), device will detect stall and the STALL, STL and
FAULT bits are latched high in the SPI register. To indicate stall detection fault on the nFAULT pin, the STL_REP
bit in CTRL5 register has to be '1'. When the STL_REP bit is '1', the nFAULT pin will be driven low when stall is
detected. In stalled condition, the motor shaft does not spin. The motor starts to spin again when the stall
condition is removed. The nFAULT line is released and the fault registers are cleared when a clear faults
command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse.
TRQ_CNT gets calculated as an average from the latest four electrical half-cycles. Once calculated, it gets
updated in the SPI register within 100 ns. After the latest TRQ_CNT is updated, it retains the value in the SPI
register for the next electrical half-cycle, after which the TRQ_CNT is updated with a new value. The duration of
the electrical half-cycle is dependent on microstepping and step-frequency. At the most, it takes two electrical
cycles to detect stall.
DRV8889-Q1
SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020
www.ti.com
36
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