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BQ79600-Q1 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ79600-Q1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 71 page  over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tHB_PERIO D HEARTBEAT: Period between HEARTBEAT Burst (from the beginning of a HEARTBEAT to the beginning of the next HEARTBEAT) 360 400 440 ms tHB_TIMEO UT HEARTBEAT: Timeout to considered as not receving HEARTBEAT 0.9 1 1.1 s tHB_FAST HEARTBEAT: If HEARTBEAT is received within this time, it is considered receving HEARTBEAT too fast 200 ms tFTONE_PE RIOD Defined by BQ7961X, FAULT TONE: Period between FAULT TONE Burst From the beginning of a FAULT TONE to the beginning of the next FAULT TONE 50 ms tFT_LATEN CY Fault Tone latency in Base Device From the time device receives the tone to the time asserts NFAULT 24 µs I/O TIMING (TX, RX, NFAULT) tRISE_TX Rise Time CLOAD = 100pF, VIO=3.3V or 5V 15 ns tFALL_TX Fall Time CLOAD = 100pF, VIO=3.3V or 5V 15 ns tFALL/ RISE_RX RX pin rise/fall time 100 ns UART TIMING UARTER R_BAUD UART TX/RX baud rate (either 250K or 1Mbps) error –1.5 1.5 % tUART(CLR ) UART Comm Clear low time 15 20 bit period tUART(RX_ HIGH) UART high time after Comm Clear, before sending Clear or Reset 1 bit period SPI TIMING SCLK SPI clock freq 2 6 MHz nSPI(CLR) SPI Comm Clear low time 8 bit tSPI_R SPI clock rising edge 25% to 75% 10 ns tSPI_F SPI clock falling edge 25% to 75% 10 ns tSPI_CLKH SPI clock high time 70 ns tSPI_CLKL SPI clock low time 70 ns t8 Max SPI_RDY service interval. This time doesn't apply if total response bytes (payload + overhead) is less than 256 bytes Read SCLK = 6MHz, with 30% SPI BUS idle time 1 ms t9 From nCS (25%) to SCLK rising (75%) 500 ns t10 From SCLK falling (25%) to nCS (75%) 500 ns t11 From nCS rising(75%) to nCS falling(25%) Don't drop nCS while SPI_RDY is low 1 µs t12 From nCS falling (25%) to stable MISO(L:20% H:80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns t13 From SCLK falling (25%) to stable MISO(L:20% H:80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns t14 From nCS rising (75%) to MISO drive to '1' (80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns tSU Setup time, refer to 75% of SCLK rising 20 ns tH Hold time, refer to 75% of SCLK rising 20 ns SNIFF DETECTOR BQ79600-Q1 SLUSDS1A – NOVEMBER 2019 – REVISED AUGUST 2020 www.ti.com 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ79600-Q1 |
Similar Part No. - BQ79600-Q1_V01 |
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Similar Description - BQ79600-Q1_V01 |
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