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IMX8MNIEC Datasheet(PDF) 63 Page - NXP Semiconductors |
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IMX8MNIEC Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 89 page  Electrical characteristics i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020 NXP Semiconductors 63 Figure 41. SAI timing—Master modes Table 55. Slave mode SAI timing (50 MHz)1 1 TX does not support 50 MHz operation in Slave mode. Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 20 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 2 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S17 SAI_RXD setup before SAI_BCLK 2 — ns S18 SAI_RXD hold after SAI_BCLK 2 — ns Table 56. Slave mode SAI timing (25 MHz) Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 40 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 12 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S15 SAI_BCLK to SAI_TXD/SAI_FS output valid — 7 ns S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 — ns S17 SAI_RXD setup before SAI_BCLK 12 — ns S18 SAI_RXD hold after SAI_BCLK 2 — ns |
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