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NTP53X2 Datasheet(PDF) 59 Page - NXP Semiconductors |
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NTP53X2 Datasheet(HTML) 59 Page - NXP Semiconductors |
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59 / 133 page  NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 59 / 133 Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 Description 1FFh N/A C0 C1 00h PROT Counter In the pass-through mode, READ and WRITE SRAM commands should be used to transfer data between the two interfaces. After POR the SRAM can be pre-loaded with default data (e.g. NDEF message) depending on SRAM_COPY_ENABLE bit in CONFIG register. If SRAM_COPY_ENABLE bit and SRAM_ENABLE both are set to 1b, then the copy feature will be triggered after POR. The startup time depends upon the number of bytes (maximum 64) to be copied. In the table below, an example is illustrated where 48 bytes are copied to the SRAM on POR. Table 108. SRAM mirroring with default content Block Byte 0 Byte 1 Byte 2 Byte 3 Description 0 SRAM_DEF00 SRAM_DEF01 SRAM_DEF02 SRAM_DEF03 : ...SRAM_DEF... 11 SRAM_DEF44 SRAM_DEF45 SRAM_DEF46 SRAM_DEF47 When SRAM is mirrored and SRAM_COPY_BYTES is equal to 30h, 48 bytes will be copied to SRAM after POR automatically 12 SRAM : : : : : 63 SRAM Rest of mirrored SRAM will be random data 64 EEPROM : : : : : From block 64 onwards again EEPROM will be addressed 510 EEPROM 511 C0 C1 00h PROT Counter Table 109. SRAM COPY BYTES (SRAM_COPY_BYTES) Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 3Ch 103Ch WDT_CONFIG WDT_ENABLE SRAM_COPY_BYTES Table 110. SRAM_COPY_BYTES Definition Bit Name Description 7 to 6 RFU RFU 5 to 0 SRAM_COPY_BYTES 6-bit length field. Defines the number of bytes (SRAM_COPY_BYTES + 1) to be copied from CONFIG memory to SRAM at startup. Maximum is 3Fh. Higher values are RFU. Default all bits are 0b. |
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