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AS7C33128NTF18B Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

Part No. AS7C33128NTF18B
Description  3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD
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Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
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AS7C33128NTF18B Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation

 
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April 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33128NTF18B
4/28/05, v 1.0
Alliance Semiconductor
P. 1 of 19
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTDTM
Features
• Organization: 131,072 words × 18 bits
•NTDarchitecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-75
-80
-10
Units
Minimum cycle time
8.5
10
12
ns
Maximum clock access time
7.5
8.0
10
ns
Maximum operating current
260
230
200
mA
Maximum standby current
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
mA
Address
D
Q
CLK
register
Output
buffer
DQ [a,b]
17
17
CLK
CE0
CE1
CE2
A[16:0]
OE
CEN
Control
CLK
logic
Data
D
Q
CLK
input
register
18
18
OE
128K x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
Q
D
ADV / LD
LBO
burst logic
addr. registers
Write delay
17
ZZ
CLK
18
18
18
18


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