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74HC240 Datasheet(PDF) 3 Page - Silicon Supplies

Part No. 74HC240
Description  High Speed CMOS Logic
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Manufacturer  SS [Silicon Supplies]
Direct Link  https://siliconsupplies.com/
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74HC240 Datasheet(HTML) 3 Page - Silicon Supplies

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PARAMETER
SYMBOL
MIN
MAX
UNITS
DC Supply Voltage
VCC
2
6
V
DC Input or Output Voltage
VIN ,VOUT
0
VCC
V
Operating Temperature Range
TJ
-40
+85
°C
VCC = 4.5V
0
1000
VCC = 5.5V
0
500
Input Rise or Fall rate
VCC = 6.0V
tr, tf
0
400
ns
 
Recommended Operating Conditions3 (Voltages referenced to GND)
Absolute Maximum Ratings1
PARAMETER
SYMBOL
VALUE
UNIT
DC Supply Voltage (Referenced to GND)
VCC
-0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
VIN
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
VOUT
-0.5 to VCC +0.5
V
DC Input Current, per pin
IIN
±20
mA
DC Output Current, per pin
IOUT
±35
mA
DC VCC or GND Current, per pin
ICC
±75
mA
Power Dissipation in Still Air
2
PD
750
mW
Storage Temperature Range
TSTG
-65 to 150
°C
 
High Speed CMOS Logic – 74HC240
Rev 1.0
29/07/20
1.  Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may
reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method.
Pad Descriptions
ADDRESS INPUTS
1A1, 1A2, 1A3, 1A4, 2A1, 2A2, 2A3, 2A4
(Pads 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROL INPUTS
1OE, 2OE (Pads 1, 19)
Output enables (active–low). When a low level is applied to these pins, the outputs are enabled and the devices function as non-
inverting buffers. When a high level is applied, the outputs assume the high impedance state.
OUTPUTS
1Y1, 1Y2, 1Y3, 1Y4, 2Y1, 2Y2, 2Y3, 2Y4
(Pads 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the output– enable pins, these outputs are either inverting outputs or high–impedance
outputs.
3.  This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT
should be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
GND or VCC). Unused outputs must be left open.


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