Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AS7C251MNTF18A Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation

Part No. AS7C251MNTF18A
Description  2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
Download  18 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
Logo 

AS7C251MNTF18A Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation

Zoom Inzoom in Zoom Outzoom out
 6 / 18 page
background image
®
AS7C251MNTF18A
12/23/04, v 1.1
Alliance Semiconductor
P. 6 of 18
Burst order
Synchronous truth table[5,6,7,8,9,11]
Key: X = Don’t Care, H = HIGH, L = LOW.
BWn = H means all byte write signals (BWa, BWb) are HIGH. BWn = L means one or more byte write
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins).
6 All inputs except
OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low in this truth table.
Interleaved burst order (LBO = 1)
Linear burst order (LBO = 0)
A1A0 A1A0 A1A0 A1A0
A1A0 A1A0 A1A0 A1A0
Starting address
0 0
0 1
1 0
1 1
Starting Address
0 0
0 1
1 0
1 1
First increment
0 1
0 0
1 1
1 0
First increment
0 1
1 0
1 1
0 0
Second increment
1 0
1 1
0 0
0 1
Second increment
1 0
1 1
0 0
0 1
Third increment
1 1
1 0
0 1
0 0
Third increment
1 1
0 0
0 1
1 0
CE0 CE1 CE2 ADV/LD R/W
BWn
OE CEN
Address
source
CLK
Operation
DQ
Notes
H
X
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
H
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
L
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
X
H
X
X
X
L
NA
L to H
CONTINUE DESELECT Cycle
High-Z
1
L
H
L
L
H
X
L
L
External L to H
READ Cycle (Begin Burst)
Q
X
X
X
H
X
X
L
L
Next
L to H
READ Cycle (Continue Burst)
Q
1,10
L
H
L
L
H
X
H
L
External L to H NOP/DUMMY READ (Begin Burst) High-Z
2
X
X
X
H
X
X
H
L
Next
L to H
DUMMY READ (Continue Burst)
High-Z 1,2,10
L
H
L
L
L
L
X
L
External L to H
WRITE CYCLE (Begin Burst)
D
3
X
X
X
H
X
L
X
L
Next
L to H
WRITE CYCLE (Continue Burst)
D
1,3,10
L
H
L
L
L
H
X
L
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
2,3
X
X
X
H
X
H
X
L
Next
L to H
WRITE ABORT (Continue Burst)
High-Z
1,2,3,
10
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
4


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18 


Datasheet Download



Related Electronics Part Number

Part NumberComponents DescriptionHtml ViewManufacturer
AS7C25512NTF32A2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C3364NTF32B3.3V 64K x 32/36 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C251MNTF32A2.5V 1M x 32/36 Flowthrough SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33128NTF18B3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33128NTF32B3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33256NTF18B3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33256NTF32A3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33512NTF18A3.3V 512K x 18 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C33512NTF32A3.3V 512K x 32/36 Flowthrough Synchronous SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation
AS7C252MNTF18A2.5V 2M x 18 Flowthrough SRAM with NTD 1 2 3 4 5 MoreAlliance Semiconductor Corporation

Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn