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74LVQ20 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. 74LVQ20
Description  DUAL 4-INPUT NAND GATE
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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74LVQ20 Datasheet(HTML) 1 Page - STMicroelectronics

   
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July 2001
s
HIGH SPEED:
tPD = 5.3 ns (TYP.) at VCC = 3.3 V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
ICC = 2µA(MAX.) at TA=25°C
s
LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s
75
Ω TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ20 is a low voltage CMOS DUAL
4-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ20
DUAL 4-INPUT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LVQ20M
74LVQ20MTR
TSSOP
74LVQ20TTR
TSSOP
SOP


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