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IS41LV16105 Datasheet(PDF) 8 Page - Integrated Circuit Solution Inc |
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IS41LV16105 Datasheet(HTML) 8 Page - Integrated Circuit Solution Inc |
8 / 18 page IS41C16105 IS41LV16105 8 Integrated Circuit Solution Inc. DR005-0C AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. Units tACH Column-Address Setup Time to CAS 15 15 ns Precharge during WRITE Cycle tOEH OE Hold Time from WE during 8 10 ns READ-MODIFY-WRITE cycle(18) tDS Data-In Setup Time(15, 22) 0 0 ns tDH Data-In Hold Time(15, 22) 8 10 ns tRWC READ-MODIFY-WRITE Cycle Time 108 133 ns tRWD RAS to WE Delay Time during 64 77 ns READ-MODIFY-WRITE Cycle(14) tCWD CAS to WE Delay Time(14, 20) 26 32 ns tAWD Column-Address to WE Delay Time(14) 39 47 ns tPC Fast Page Mode READ or WRITE 20 25 ns Cycle Time(24) tRASP RAS Pulse Width 50 100K 60 100K ns tCPA Access Time from CAS Precharge(15) 30 35 ns tPRWC READ-WRITE Cycle Time(24) 56 68 ns tCOH Data Output Hold after CAS LOW 5 5 ns tOFF Output Buffer Turn-Off Delay from 1.6 121.6 15 ns CAS or RAS(13,15,19, 29) tWHZ Output Disable Delay from WE 310 3 10 ns tCLCH Last CAS going LOW to First CAS 10 10 ns returning HIGH(23) tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5 5 ns tCHR CAS Hold Time (CBR REFRESH)(30, 21) 8 10 ns tORD OE Setup Time prior to RAS during 0 0 ns HIDDEN REFRESH Cycle tREF Auto Refresh Period (1,024 Cycles) 16 16 ms tT Transition Time (Rise or Fall)(2, 3) 150 1 50 ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%) One TTL Load and 50 pF (Vcc = 3.3V ±10%) Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%); VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%) |
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