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7025E Datasheet(PDF) 6 Page - Maxwell Technologies

Part No. 7025E
Description  (8K x 16-Bit) Dual Port RAM High-Speed CMOS
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Maker  MAXWELL [Maxwell Technologies]
Homepage  http://www.maxwell.com
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7025E Datasheet(HTML) 6 Page - Maxwell Technologies

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©2002 Maxwell Technologies
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(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
08.15.02 Rev 2
TABLE 9. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION
(V
CC = 5V ± 10%, VSS = 0V, TA = -55 TO 125
°
C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
For Master Only
BUSY Access Time to Address Match
-35
-45
t
BAA
--
--
35
35
ns
BUSY Disable Time to Address Not Matched
-35
-45
t
BDA
--
--
30
30
ns
BUSY Access Time to Chip Select Low
-35
-45
t
BAC
--
--
30
30
ns
BUSY Disable Time to Chip Select High
-35
-45
t
BDC
--
--
25
25
ns
Write Pulse to Data Delay 1
-35
-45
1. Port to port timing delay through RAM cells from writing port to reading port.
t
WDD
--
--
60
70
ns
Write Data Valid to Read Data Delay 1
-35
-45
t
DDD
--
--
45
55
ns
Arbitration Priority Setup Time 2
-35
-45
2. To ensure that the earlier of the two ports wins.
t
APS
5
5
--
--
ns
BUSY Disable to Valid Data
-35
-45
t
BDD
--
--
3
3
3. t
BDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tWD (actual).
ns
For Slave Only
Write to BUSY Input 4
4. To ensure that the write cycle is inhibited during contention.
t
WB
0--
ns
Write Hold after BUSY 5
5. To ensure that a write cycle is completed after contention.
t
WH
25
--
ns
Write Pulse to Data Delay 1
-35
-45
t
WDD
--
--
60
70
ns
Write Data Valid to Read Data Delay 1
-35
-45
t
DDD
--
--
45
55
ns


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