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97SD3240RPQK Datasheet(PDF) 5 Page - Maxwell Technologies |
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97SD3240RPQK Datasheet(HTML) 5 Page - Maxwell Technologies |
5 / 39 page 97SD3240 5 All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM 02.04.05 Rev 3 TABLE 5. AC Electrical Characteristics (V CC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL SUBGROUPS MIN TYPICAL MAX UNIT System clock cycle time1 (CAS latency = 2) (CAS latency = 3) t CK 9, 10, 11 10 7.5 ns CLK high pulse width1,7 t CKH 9, 10, 11 2.5 ns CLK low pulse width1,7, t CKL 9, 10, 11 2.5 ns Access time from CLK1,2 (CAS latency = 2) (CAS latency = 3) t AC 9, 10, 11 6 6 ns Data-out hold time1,2,3 t OH 9, 10, 11 2.7 ns CLK to Data-out low impedance1,2,3,7 t LZ 9, 10, 11 2 ns CLK to Data-out high impedance1,47, (CAS latency = 2, 3) t HZ 9, 10, 11 5.4 ns Input setup time1,5,6 t AS, tCS, t DS, tCES 9, 10, 11 1.5 ns CKE setup time for power down exit1 t CESP 9, 10, 11 1.5 ns Input hold time1,6 t AH, tCH, tDH t CEH 9, 10, 11 1.5 ns Ref/Active to Ref/Active command period1 t RC 9, 10, 11 70 ns Active to Precharge command period1 t RAS 9, 10, 11 50 120000 ns Active command to column command 1 (same bank) t RCD 9, 10, 11 20 ns Precharge to Active command period1 t RP 9, 10, 11 20 ns Write recovery or data-in to precharge lead time1 t DPL 9, 10, 11 20 ns Active( a) to Active (b) command period1 t RRD 9, 10, 11 20 ns Transition time(rise and fall)7 t T 9, 10, 11 1 5 ns Refresh Period t REF 9, 10, 11 16 6.4 ms @ 105 °C32 168 @ 85 °C64 @ 70 °C 128 1. AC measurement assumes t T=1ns. Reference level for timing of input signals is 1.5V. 2. Access time is measured at 1.5V. 3. t LZ(min) definesthe time at which the outputs achieve the low impedance state. 4. t HZ(min) defines the time at which the outputs achieve the high impedance state. 5. tCES defines CKE setup time to CLK rising edge except for the power down exit command. 6. t AS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM 7. Guarenteed by design (Not tested). 8. Guarenteed by Device Charactreization Testing. (Not 100% Tested) |
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