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FMS9874KGC100 Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FMS9874KGC100 Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 25 page  FMS9874 PRODUCT SPECIFICATION REV. 1.5 11/10/00 9 Figure 3. Internal Sampling Clock, SCK Timing PHASE Sn PXCK/XCK SCK VIN DCK DA Ideally, incoming pixels would be trapezoidal with fast rise- times and the sampling edge of the A/D clock, SCK would be positioned along the level section of the incoming pixel waveform as shown in Figure 4. There is a narrow zone of uncertainly where sampling during pixel rise time would cause an error in the value of the A/D data output, D7-0, which is shown as a value, 0-255. Figure 4. Ideal Pixel Sampling In practice, high-resolution pixels have long rise-times. As shown in Figure 5, there are narrow zones of serendipity when the pixel amplitude is level. Samples are valid in these zones. Figure 5. Acceptable Pixel Sampling Referring to Figure 6, when the sample clock, SCK has some jitter, if the sampling edge occurs anywhere within the zone of uncertainty where the pixel rise time is steep, there will be amplitude modulation of the digitized data, D7-0, due to the sampling clock jitter. To avoid corruption of the image, set- ting the value PHASE7-0 is critical. PHASE4-0 should be trimmed to position the sampling edge of SCK within the zone of serendipity. Figure 6. Improper Pixel Sampling Voltage References An on-chip voltage reference is generated from a bandgap source. VREFOUT is the buffered output of this source that can be connected to VREFIN to supply a voltage reference that is common to the three converter channels. VREFIN, with a nominal voltage of 1.25V, is the source of the differential reference voltages for each A/D converter. Reference voltages supplied to the differential inputs of the comparators in the A/D converters are derived from VREFIN. Digital Data Outputs Input horizontal sync HSIN and outgoing data, D[7..0] are resynchronized to the delayed sample clock, SCK. Output timing characteristics are defined in Figure 4. Latency of the first pixel, N varies according to the mode: 1. Normal. 2. Alternate pixel sampling. Levels are 3.3 volt CMOS with the output supply variable between 2.5 and 3.3 V. PWRDN = L sets the outputs high-impedance. PWRDN = H enables the outputs. D7-0 RIN, GIN, BIN SCK Zones of Uncertainty D7-0 RIN, GIN, BIN SCK Zones of Serendipity D7-0 RIN, GIN, BIN SCK Zones of Uncertainty |
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