TM2SN64EPU 2097152 BY 64-BIT

TM4SN64EPU 4194304 BY 64-BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS681 – AUGUST 1997

9

POST OFFICE BOX 1443

’xSN64EPU-12A‡

’xSN64EPU-12

UNIT

MIN

MAX

MIN

MAX

UNIT

tAC2

Access time, CK high to data out, CAS latency = 2 (see Note 8)

9

10

ns

tAC3

Access time, CK high to data out, CAS latency = 3 (see Note 8)

9

9

ns

tCK2

Cycle time, CK, CAS latency = 2

15

18

ns

tCK3

Cycle time, CK, CAS latency = 3

12

12

ns

tLZ

Delay time, CK high to DQ in low-impedance state (see Note 9)

3

3

ns

tHZ

Delay time, CK high to DQ in high-impedance state (see Note 10)

10

10

ns

tRAS

Delay time, ACTV command to DEAC or DCAB command

60

100 000

72

100 000

ns

tRC

Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR

command

90

108

ns

tRCD

Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command

(see Note 11)

30

30

ns

tRP

Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command

30

36

ns

tRRD

Delay time, ACTV command in one bank to ACTV command in the other bank

24

24

ns

tRSA

Delay time, MRS command to ACTV, MRS, REFR, or SLFR command

24

24

ns

tAPR

Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command

tRP – (CL –1)

∗ tCK

ns

tOH

Hold time, CK high to data out

3

3

ns

tIH

Hold time, address, control, and data input

1

1.5

ns

tCESP Power down/self-refresh exit time

10

10

ns

tCH

Pulse duration, CK high

4

4

ns

tCL

Pulse duration, CK low

4

4

ns

tIS

Setup time, address, control, and data input

3

3

ns

tAPW

Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command

60

60

ns

tWR

Delay time, final data in of WRT operation to DEAC or DCAB command

15

20

ns

tT

Transition time (see Note 12)

1

5

1

5

ns

tREF

Refresh interval

64

64

ms

nCCD

Delay time, READ or WRT command to an interrupting command

1

1

cycle

nCDD

Delay time, CS low or high to input enabled or inhibited

0

0

0

0

cycle

nCLE

Delay time, CKE high or low to CK enabled or disabled

1

1

1

1

cycle

nCWL

Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P

1

1

cycle

nDID

Delay time, ENBL or MASK command to enabled or masked data in

0

0

0

0

cycle

nDOD

Delay time, ENBL or MASK command to enabled or masked data out

2

2

2

2

cycle

nHZP2

Delay time, DEAC or DCAB command to DQ in high-impedance state,

CAS latency = 2

2

2

cycle

nHZP3

Delay time, DEAC or DCAB command to DQ in high-impedance state,

CAS latency = 3

3

3

cycle

nWCD Delay time, WRT command to first data in

0

0

0

0

cycle

† All references are made to the rising transition of CK unless otherwise noted.

‡ -12A speed device is supported only at – 5% to +10% VDD

NOTES:

8. tAC is referenced from the rising transition of CK that is previous to the data-out cycle. For example, the first data out tAC is referenced

from the rising transition of CK that is CAS latency – one cycle after the READ command. Access time is measured at output

reference level 1.4 V.

9. tLZ is measured from the rising transition of CK that is CAS latency – one cycle after the READ command.

10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.

11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.

12. Transition time, tT, is measured between VIH and VIL.