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MAX5621UCB Datasheet(PDF) 12 Page - Maxim Integrated Products

Part No. MAX5621UCB
Description  16-Bit DACs with 16-Channel
Download  16 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5621UCB Datasheet(HTML) 12 Page - Maxim Integrated Products

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Figure 6 shows an example of a burst mode operation.
As with the immediate update example,
CS falls while
channel 7 is being refreshed. Data for multiple chan-
nels is loaded, and no channels are refreshed as long
as
CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
operation. Thirty-three fSEQ cycles are required before
all channels have been updated.
External Sequencer Clock
An external clock can be used to control the
sequencer, altering the output update rate. The
sequencer runs at 1/4 the frequency of the supplied
clock (ECLK). The external clock option is selected by
driving either C0 or CLKSEL high.
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy sys-
tem measurements. The low 1mV/s droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F2C hex) in sequence, requiring 320µs. This pre-
vents damage to downstream ICs due to arbitrary refer-
ence levels being presented following system power-up.
This same function is available by driving
RST low.
During the reset operation, the sequencer is run by the
internal clock, regardless of the state of CLKSEL. The
reset process cannot be interrupted, and serial inputs
are ignored until the entire reset process is complete.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals may couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the VDD, VSS,
and VL_ pins. They should be placed as close to the
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5621/MAX5622/MAX5623 have three separate
+5V logic power supplies, VLDAC, VLOGIC, and VLSHA.
VLDAC powers the 16-bit digital-to-analog converter,
VLSHA powers the control logic of the SHA array, and
VLOGIC powers the serial interface, sequencer, internal
clock and SRAM. Additional filtering of VLDAC and
VLSHA improves the overall performance of the device.
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
12
______________________________________________________________________________________
SKIP
6
7
SKIP
SKIP
7
8
5
6
CS
DIN
33/fSEQ TO UPDATE
ALL CHANNELS
2/fSEQ
LOAD MULTIPLE
ADDRESSES
SHA ARRAY
UPDATE
SEQUENCE
7
Figure 6. Burst Mode Timing Example
Figure 7. Typical Operating Circuit
CS
DIN
SCLK
IMMED
CLKSEL
REF
GS
RST
ECLK
VLOGIC VLDAC VLSHA
0.1µF
+5V
0.1µF
+10V
VDD
MAX5621
MAX5622
MAX5623
OUT15
OUT0
OUT1
DGND
AGND
0.1µF
VSS
CL
+2.5V
-4V


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