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IC41C82052-50J Datasheet(PDF) 7 Page - Integrated Circuit Solution Inc |
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IC41C82052-50J Datasheet(HTML) 7 Page - Integrated Circuit Solution Inc |
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7 / 18 page  IC41C82052 IC41LV82052 Integrated Circuit Solution Inc. 7 DR015-0A 06/12/2001 AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. Units tACH Column-Address Setup Time to CAS 15 15 ns Precharge during WRITE Cycle tOEH OE Hold Time from WE during 8 10 ns READ-MODI.Y-WRITE cycle(18) tDS Data-In Setup Time(15, 22) 0 0 ns tDH Data-In Hold Time(15, 22) 8 10 ns tRWC READ-MODI.Y-WRITE Cycle Time 108 133 ns tRWD RAS to WE Delay Time during 64 77 ns READ-MODI.Y-WRITE Cycle(14) tCWD CAS to WE Delay Time(14, 20) 26 32 ns tAWD Column-Address to WE Delay Time(14) 39 47 ns tPC EDO Page Mode READ or WRITE 20 25 ns Cycle Time tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns tCPA Access Time from CAS Precharge(15) 30 35 ns tPRWC EDO Page Mode READ-WRITE 56 68 ns Cycle Time tCOH Data Output Hold after CAS LOW 5 5 ns tO.. Output Buffer Turn-Off Delay from 0 12 0 15 ns CAS or RAS(13,15,19, 24) tWHZ Output Disable Delay from WE 310 3 10 ns tCSR CAS Setup Time (CBR RE.RESH)(20, 25) 5 5 ns tCHR CAS Hold Time (CBR RE.RESH)( 21, 25) 8 10 ns tORD OE Setup Time prior to RAS during 0 0 ns HIDDEN RE.RESH Cycle tRE. Auto Refresh Period 2,048 Cycles 32 32 ms tT Transition Time (Rise or .all)(2, 3) 150 1 50 ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 p. (Vcc = 5.0V + 10%) One TTL Load and 50 p. (Vcc = 3.3V + 10%) Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%) VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%) |
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